1. Field of the Invention
The present invention relates generally to signal multiplexing on an interface bus, and in particular, to a method and apparatus for multiplexing PCI bus connector signals with sideband signals.
2. Description of Related Art
The Peripheral Component Interconnect (PCI) local bus is a high performance 32 or 64 bit bus with multiplexed address and data lines. The PCI Local Bus Specification, Rev. 2.0, incorporated by reference herein, defines the protocol, electrical, mechanical, and configuration specifications for PCI Local Bus components and expansion boards. The PCI local bus defines an industry standard high performance low cost local bus architecture. The PCI component and add-in card interface is also processor independent, enabling an efficient transition to future processor generations and ensuring compatibility with multiple processor architectures. The processor independence allows the PCI local bus to be optimized for input/output (I/O) functions, enabling concurrent operations of the local bus with the processor/memory subsystem, and accommodating multiple high performance peripherals in addition to graphics such as motion video, LAN, SCSI, FDDI, hard disk drives. High bandwidth I/O items such as enhanced video, multi-media displays and high definition TV, will continue to increase local bus bandwidth requirements. The PCI interface supports high bandwidth I/O, and is therefore highly suited to these applications. The PCI interface is also particularly useful for interconnecting high integrated peripheral controller components, peripheral add-in boards, and processor/memory systems.
The PCI interface standard offers other benefits as well. Configuration registers are specified for PCI components than add-in cards. A system with embedded auto configuration software offers true ease of use for the system user by automatically configuring PCI add-in cards at power on.
One limitation of the PCI local bus is that the PCI connector has no pins for sideband signals. Without sideband signal pins, sideband signals cannot be implemented directly on the interface connector. Sideband signals are loosely defined as any signal not part of the PCI specification that connects two or more PCI compliant agents, and has meaning only to these agents. Sideband signals may be used for two or more devices to communicate some aspect of their device-specific state in order to improve the overall effectiveness of PCI utilization or system operation. Flush request and acknowledge signals are used as an example here, but the present invention could be applied to any other two additional pin requirements on a PCI connector. For example, the present invention could be used to extend two data bus signals of the Interrupt Controller Communication (ICC) bus for Intel's APIC (Advanced Programmable Interrupt Controller). New system designs may need to connect an existing legacy bus such as an EISA/ISA or MCA through several hierarchical PCI bridges, typically mounted on a PCI add-in card rather than in a plenary implementation such as a motherboard. Since a legacy bus usually lacks a back-off capability, at least two sideband signals, flush request and flush acknowledge, must be routed throughout the bus hierarchy (from a legacy bus to a host bridge) to avoid deadlock. Deadlock may occur when a downstream operation to the legacy bus module and an upstream operation from that legacy bus module are initiated concurrently. Normally, these signals would be provided by sideband signals. As mentioned earlier, the standard PCI interface does not provide sideband signaling capability. The present invention solves this problem by multiplexing these sideband signals in the PRSNT 1# and PRSNT 2# signals of the standard PCI connector.